Electromigration behavior of dual-damascene Cu interconnects––Structure, width, and length dependences

Abstract

Experiments were performed to study the effect of line width and length, and the results revealed interesting differences in electromigration behavior of via-fed upper and lower layer dual-damascene test structures. The observed location of electromigration induced void in upper and lower layer test structures cannot be completely explained by the theory of current gradient induced vacancy diffusion. The electromigration median time to failure (MTF) were found to be dependent upon the line width for the lower layer test structures while it remained unaffected in the case of upper layer test structure. Cu/dielectric cap interface acting as the dominant electromigration path and the current crowding location being near the Cu/dielectric cap interface for lower layer structures due to structural differences, explain this behavior. Similarly, short length upper and lower layer test structures exhibited completely different characteristics. The back stress effect on short lines was evident on both upper and lower layer structures, however, only the upper layer showed two distinct via and line failure mechanisms. These observed effects are specific to Cu dual-damascene structures and can have major technological implications for electromigration reliability assessment.