Electromigration and Power Analysis of Digital Circuits at 10 nm Technology Node Before Signoff

Abstract

With modern advancements in technology nodes and increasing design density, it is becoming more challenging to handle integrity and reliability checks as signoff verification steps. Electromigration (EM), IR drop, and power analysis play an important role as verification reliability signoff measures for any integrated circuits (ICs). As we step forward into advance technology nodes, the interconnect wire width becomes thinner along with transistor size. This makes the wire resistance more dominant at advance technology nodes like 10 nm and 7 nm. This increasing resistance introduces high IR drop and power issues which play significant role in the functionality failure of any electronic device with lower process technology nodes. Due to failures in hardware and functionality, more time and efforts are required for signoff. Electromigration analysis has also become a critical task due to technology scaling and increasing current density in small cross section area of routing wires. This work explores performance analysis in electromigration, voltage drop and power analysis using Redhawk tool. This work also discusses the factors affecting electromigration, voltage drop and power analysis and also the possible solutions to mitigate violations at signoff and in between physical designing stages.