Electrolytic solder deposit for next generation flip chip solder bumping: 2010 International Microsystems, Packaging, Assembly and Circuits Technology (IMPACT) conference

Abstract

Current methods for the formation of pre-solder bumps for flip chip attachment use stencil printing techniques with an appropriate solder paste. The continuing trend towards increasing miniaturisation and the associated decrease in size of solder resist opening, SRO is causing production difficulties in particular associated with achieving sufficient yields with the stencil printing process. Practical experience of current production yields has shown that stencil printing will not be able to meet future requirements for solder bump pitch production below 0.15 mm for these applications. Also the increased costs associated with low yields are an ever present factor. This paper describes a novel approach to replace the stencil printing process by use of an electrolytic deposition of solder. In contrast to stencil printing, use of electrolytic deposition techniques allows production of solder bumps with a pitch below 0.15 mm and with a SRO below 80 jim. The electrolytic deposition of tin requires an electrical connection to each surface for metal deposition; this process is shown as made using an appropriate copper seed layer which is produced onto the structured soldermask. Specially modified activation and electroless copper processes are introduced for this critical process step. Following this the use of a photo sensitive plating resist defines the SRO which is then filled with the electrolytic tin deposit. The associated processes required both for seed layer production and for removal of plating resist and subsequent etching of the seed layer are described and first qualification results are shown from the complete process. Methods for production of electrolytic solder bumps based on pure tin as well as alloys of tin/copper are shown and in particular a method to control the alloy concentration of electroplated tin/copper bumps. Test results with both alloy system and also pure tin bumping are presented together with comparison of the advantages and disadvantages. This newly developed Sn/Cu plating process allows for a simultaneous plating of both sides of IC Substrates, the C4 and the BGA side of the panel. On the C4 side the complete Sn/Cu solder ball is plated whereas on the BGA side the basis for the subsequent placement of a larger solder ball can be achieved. Examples are given for such a process flow using the photo resist process on top of a solder resist. As a further development of the solder bumping process the photo resist free sequence is introduced which uses a modified tin deposition electrolyte to produce tin filled structures directly onto the structured and prepared soldermask. This process offers optimum solder bump plated distribution and the potential for further cost savings due to the elimination of critical processing steps associated with photo imaging.