Electrode Design to Overcome Substrate Transparency Limitations for Highly Efficient 1 cm2 Mesoscopic Perovskite Solar Cells

Abstract

•New electrode design enables large-area mesoscopic device on ITO substrates•Design principle, simulation method for cell geometry optimization•Balancing conductivity and transmittance by varying ITO thickness•Record efficiency for 1 cm2 perovskite solar cell fabricated by gas quenching Mesoscopic cell structure and fluorine-doped tin oxide (FTO) glass have been the architect and substrate of choice, respectively, for state-of-the-art perovskite solar cells (PSCs). Although ITO is optical superior to FTO, the high-temperature annealing required for the fabrication of TiO2 layers causes conductivity loss in the ITO. Herein, we introduce a new electrode design for large-area perovskite (>1 cm2) on high-transparency, low-conductivity ITO substrate compatible with high-temperature processing of mesoscopic structure. We demonstrate cells with improved photocurrent without sacrificing fill factor, outperforming cells on FTO substrates. By further optimizing device geometry and ITO thickness guided by simulation, a certified 19.6% efficiency is achieved on ITO-based mesoscopic PSCs. This work overcomes the limitations of substrate choice for mesoscopic PSCs, benefitting the development of high-efficiency, large-area PSCs. Fluorine-doped tin oxide glass substrate is typically used for state-of-the-art perovskite solar cells (PSCs). However, indium-doped tin oxide (ITO) is better due to higher transparency for a given conductivity, although it has lower tolerance to high-temperature processes required for the compact and mesoporous TiO2 layers. Here we overcome this challenge by developing and utilizing a new electrode design. We successfully demonstrate high-efficiency mesoscopic PSCs on annealed ITO substrates showing improved photocurrent without sacrificing fill factor. After further optimizations of cell geometry and substrate conductivity guided by simulation, a certified 19.63% efficiency is achieved on 1 cm2 for ITO-based mesoscopic PSC, which is the highest among PSCs prepared by gas quenching. This work is useful for providing design principles and methods for optimizing cell geometry, metal electrode design, and substrate conductivity requirements for large-area PSCs. Fluorine-doped tin oxide glass substrate is typically used for state-of-the-art perovskite solar cells (PSCs). However, indium-doped tin oxide (ITO) is better due to higher transparency for a given conductivity, although it has lower tolerance to high-temperature processes required for the compact and mesoporous TiO2 layers. Here we overcome this challenge by developing and utilizing a new electrode design. We successfully demonstrate high-efficiency mesoscopic PSCs on annealed ITO substrates showing improved photocurrent without sacrificing fill factor. After further optimizations of cell geometry and substrate conductivity guided by simulation, a certified 19.63% efficiency is achieved on 1 cm2 for ITO-based mesoscopic PSC, which is the highest among PSCs prepared by gas quenching. This work is useful for providing design principles and methods for optimizing cell geometry, metal electrode design, and substrate conductivity requirements for large-area PSCs. Organic metal lead halide perovskite solar cells (PSCs) have undergone rapid development in recent years. Small-area devices have recorded certified efficiencies that have risen from 14.1% in 2013 to 22.7%1Green M.A. Hishikawa Y. Dunlop E.D. Levi D.H. Hohl-Ebinger J. Ho-Baillie A.W.Y. Solar cell efficiency tables (version 51).Prog. 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Park B.-W. Jung E.H. Jeon N.J. Kim Y.C. Lee D.U. Shin S.S. Seo J. Kim E.K. Noh J.H. et al.Iodide management in formamidinium-lead-halide–based perovskite layers for efficient solar cells.Science. 2017; 356: 1376Crossref PubMed Scopus (4318) Google Scholar, 11Snaith H.J. Perovskites: the emergence of a new era for low-cost, high-efficiency solar cells.J. Phys. Chem. Lett. 2013; 4: 3623-3630Crossref Scopus (2307) Google Scholar However, these highly efficient mesoscopic PSCs have to rely on the use FTO substrates because the compact TiO2 (c-TiO2) and the mesoporous TiO2 (mp-TiO2) require high-temperature processes. As another widely used transparent conducting oxide (TCO), indium tin oxide (ITO) is more versatile, allowing greater transparency and resistance control and can be deposited by a wide variety of deposition methods on different substrates, while FTO requires high deposition temperature and treatment using toxic gas in its production.12Hosono H. Paine D.C. Handbook of Transparent Conductors. Springer Science & Business Media, 2010Google Scholar More importantly, ITO has a smoother surface and higher transparency at a given conductivity compared with FTO. However, a significant drawback of ITO is its poor compatibility with high-temperature heat treatment, which can drastically reduce its conductivity.13Gong J. Liang J. Sumathy K. Review on dye-sensitized solar cells (DSSCs): fundamental concepts and novel materials.Renew. Sustain. Energy Rev. 2012; 16: 5848-5860Crossref Scopus (685) Google Scholar Therefore, ITO has been used by most of the inverted p-i-n structured PSCs10Wu Y. Yang X. Chen W. Yue Y. Cai M. Xie F. Bi E. Islam A. Han L. Perovskite solar cells with 18.21% efficiency and area over 1 cm2 fabricated by heterojunction engineering.Nat. Energy. 2016; 1: 16148Crossref Scopus (523) Google Scholar, 14Malinkiewicz O. Yella A. Lee Y.H. Espallargas G.M. Graetzel M. Nazeeruddin M.K. Bolink H.J. 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High-efficiency mesoscopic devices on ITO substrate are yet to be demonstrated. Systematic study focusing on the selection and optimization of the TCO substrate is of great significance to push the short-circuit current density and PCE closer to their theoretical maximums for large-area devices. In this work, the conventionally used FTO substrate is replaced by a more transparent ITO substrate to achieve higher photocurrent. In order allow for high-temperature annealing on ITO substrates, we introduce a new electrode design that enables a more efficient cell geometry to assist current transport on substrates with lower conductivity for the fabrication of 1 cm2 mesoscopic PSCs achieving high efficiencies. All of the perovskite layer was deposited by a gas-quenching technique achieving excellent uniformity over a large area.21Zhang M. Yun J.S. Ma Q. Zheng J. Lau C.F.J. Deng X. Kim J. Kim D. Seidel J. Green M.A. et al.High-efficiency rubidium-incorporated perovskite solar cells by gas quenching.ACS Energy Lett. 2017; 2: 438-444Crossref Scopus (209) Google Scholar By optimizing the geometry of the cell in conjunction with a wrap-around electrode and by optimizing the thickness of ITO layer guided by the results of simulation, a 19.63% certified efficiency on 1.02 cm2 was achieved for the ITO-based mesoscopic PSC, which is among the highest for devices on an area larger than 1 cm2. The PSC fabricated in this study has a mesoscopic device structure, as shown by the cross-sectional scanning electron microscopy (SEM) image in Figure 1A. In this work, all perovskite film was fabricated by a one-step gas-quenching technique that is considered more reliable and reproducible in the fabrication of large-area perovskite films.21Zhang M. Yun J.S. Ma Q. Zheng J. Lau C.F.J. Deng X. Kim J. Kim D. Seidel J. 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Gas quenching for perovskite thin film deposition.Joule. 2018; 2: 1205-1209Abstract Full Text Full Text PDF Scopus (47) Google Scholar By using the gas-quenching technique, a 1 μm thick FA0.80MA0.15Cs0.05PbI2.55Br0.45 mixed cation perovskite layer on top of the 150 nm perovskite-infiltrated-mp-TiO2 layer can be uniformly deposited. Compared with the conventional electrode, which is a layer of laser-scribed ITO on glass (Figure 1A), our new electrode design for 1 cm2 devices includes a 150 nm thick gold layer in a U shape on top of the ITO (Figure 1B). The wrap-around gold layer acts as a metal grid to enhance the extraction of photo-generated electrons. The conventional electrode relies on the ITO to transport the electrons to the point where contact probing will occur, which is typically performed by soldering. With the new electrode, the wrap-around gold provides a less resistive path compared with the ITO substrate, allowing better electron transport to the contact probe. With the presence of the wrap-around gold, which acts as an “electron highway,” we can afford to use an ITO substrate with poorer conductivity, such as when high temperate annealing is essential for subsequent processes (Figure 1C). To demonstrate the effectiveness of the new electrode design on low-conductivity ITO substrate (e.g., as a result of multiple annealing at high temperature), a spatial distribution of sheet resistance (Rsheet) on 35 Ω/sq ITO is simulated with conventional (Figure 2A) and new (Figure 2B) electrode designs. The active area for a 10 × 10 mm2 cell is defined by the red dashed lines. The bold black line at the bottom of the series resistance (Rs) map is where the contact probe is. With the conventional electrode, the RS within the active is averaged at around 20 Ωcm2. With the new electrode, the RS has been reduced by the wrap-around gold to around 5 Ωcm2, which is critical for device performance. To verify the model experimentally, 10 × 10 mm2 mesoscopic PSCs using conventional electrode and new electrode were fabricated. The current density-voltage (J-V) curves of the devices are given in Figure 2B. The 1 cm2 device with the conventional electrode suffers from a low PCE of 12.2% with a poor fill factor (FF) of 50% due to the very high RS (18.6 Ωcm2, which is in good agreement with the simulated value) from the ITO substrate with reduced conductivity after annealing. Figure S1A shows the adverse effect on ITO conductivity after annealing, while Figure S1B takes into the account of the presence of c-TiO2 and mp-TiO2 under the actual annealing conditions used. The Rsheet of the ITO substrate that did not have c-TiO2 or mp-TiO2 but underwent the same thermal budget was also shown for comparison. When a new electrode design is used, device performance was greatly improved with a lower RS at 7.5 Ω cm2 (in good agreement with the simulated value) and a higher FF at 72.2% result in much higher PCE of 18.4%. This demonstrates that PSCs fabricated on a less conductive substrate can still achieve a decent device performance by employing a wrap-around metal grid design. Nevertheless, when we measure the device with new electrode design using a small-area aperture (0.159 cm2) where the output current is low, the FF ranged from 80.4% to 81.5% depending on the location where the small-area measurement was taken (Figure S2). This indicates that, even with the presence of wrap-around gold, the resistive loss is still not negligible. In order to further reduce the resistive loss and therefore further improve the efficiency of the devices, the geometry of the cell with the wrap-around gold layer needs to be redesigned. From the RS mapping of the square device (10 × 10 mm2) (on the far left of Figure 3A), we can see that the photo-generated electrons in the middle and at the top of the map have a distance to travel before they reach the nearest gold, resulting in a relatively high RS (∼7 Ωcm2) in these regions. We therefore looked at the RS distributions for a rectangular device (6 × 17 mm2) and strip device (4 × 25 mm2), which reduce the distance between the two gold fingers while keeping the same active area of 1 cm2. Results are shown in the middle and on the far right of Figure 3A, showing much-improved RS distributions, which have been effectively halved, in the best design as the distance the electrons have to be travel are effectively halved. It is interesting to note that, although the gold fingers are longer in the rectangular and strip devices, there is no increase in RS due to the excellent conductivity of gold even though it is annealed. We further simulated the photovoltaic performance to produce a J-V curve for each device based on a given short-circuit current density (JSC = 22.4 mA/cm2) and open-circuit voltage (VOC = 1,150 mV) value, which are considered achievable for FA0.80MA0.15Cs0.05PbI2.55Br0.45 mixed cation perovskite. The J-V simulated curves of each device with different geometry with wrap-around gold are presented as solid lines in Figure 3B. The rectangular device and strip device are predicted to have an FF of 75.8% and 77.4%, respectively; much higher than the FF of 71.7% for the square device. To verify the model experimentally, 6 × 17 mm2 and 4 × 25 mm2 FA0.80MA0.15Cs0.05PbI2.55Br0.45 mixed cation perovskite devices using electrodes with new geometries were fabricated (Figure S3). It should be noted that the width of the wrap-around electrodes can be further reduced as the thickness of the electrodes increases. For the purpose of showing the trends in cell performance with changes in cell dimensions, an electrode thickness of 100 nm was chosen simply due to ease and speed of fabrication. If the thickness is to be increased, for example, by 5-fold, then the width of the electrodes can be reduced by the same proportion (i.e., 5-fold) to maintain the same level of conductivity. The measured J-V curves are represented as dashed lines in Figure 3B and the corresponding performance parameters of the devices are given in the inset. Compared with the square device, the devices with skinnier geometries exhibit remarkable FF improvement. The FF of the rectangular device and strip device reaches 75.0% and 76.6%, respectively. This improves the PCE of the strip device to 20.0%. We have also varied the perovskite composition to FA0.75MA0.15Cs0.10PbI2.85Br0.15 perovskite (Figure S4), which has a slightly lower bandgap of 1.59 eV. The currents of the demonstrated devices are therefore higher at ≥23 mA/cm2. However, the VOC of these devices suffer and therefore the best device with the strip geometry exhibits a PCE of merely 19.8%. Nonetheless, an FF of 77.0% is the highest for FA0.75MA0.15Cs0.10PbI2.85Br0.15 devices even on 1 cm2. Theoretically, the FF can be further improved by reducing the width of the cell; i.e., making the cell skinnier. However, complications in processing (e.g., the challenge of obtaining a uniform perovskite film on a very long strip using the gas-quenching deposition) outweigh the potential small improvement in FF. These results show the effectiveness of varying cell geometries for large-area cells to improve performance of PSCs even on low-conductivity substrates. To illustrate this, a 4 × 25 mm2 strip device was fabricated on a conventional TEC7 FTO on glass substrate using the same processing sequence. Results from the device are compared with the results from an identical device but on an annealed ITO substrate in Figure 4A. Although the FTO-based device has a slightly higher FF than the ITO-based device, the JSC of the FTO device is 0.7 mA/cm2 lower than the ITO device, due to the poorer transmittance in FTO substrate, resulting in a PCE of 19.2% compared with the 20.0% achieved on the ITO substrate. Figure 4B shows the external quantum efficiency (EQE) spectrum of the devices. The ITO-based device exhibits higher EQE than the FTO-based device and follows the same trend in terms of transmittance improvement for the corresponding wavelengths shown in Figure S5. We also simulated the photovoltaic (PV) performance for the devices fabricated on TEC15 FTO glass, which is less conductive but more transparent than conventionally used TEC7 FTO. Results are shown in Figure 4C, suggesting that all devices with the new electrode design would benefit more if fabricated on TEC15 FTO glass than on TEC7 FTO glass. However, strip and rectangular devices based on annealed ITO substrate are still superior to any FTO-based devices due to better optical transmission, as seen in the higher JSC (y axis) achieved, resulting in better PCE (efficiency contours). Consequently, the most efficient device should be fabricated on ITO substrate when using narrow cell geometry with wrap-around metal electrode allowing less conductive and higher transparency substrate to be used to improve the photocurrent without sacrificing FF. As mentioned previously, ITO is versatile for transparency and conductivity control. Thus the device performance can potentially be further improved by optimization of ITO thickness. We vary the in-house deposited ITO thickness on borosilicate glass. The electrical and optical properties before and after high-temperature treatment are characterized. The Rsheet values are plotted in Figure 5A (blue histograms), while the transmittance spectra are given in Figure S6. The incident optical loss expressed is then calculated as the percentage of energy under the AM1.5 solar spectra not absorbed for each in-house deposited ITO substrate. The incident energy losses are plotted in Figure 5A (green histograms), which increase with ITO thickness, while Rsheet follows an opposite trend. Significant Rsheet increase can be observed after annealing, while the incident energy losses also exhibit small increases. The relatively high Rsheet of annealed ITO (>15 Ω/sq for ITO thickness of 350 nm) makes the substrate not suitable for PSCs using conventional cell geometry and conventional contacting design that relies heavily on the ITO itself for current transport. However, if a narrow cell geometry is used (a “strip” device using a wrap-around metal electrode), we can take advantage of the high transparency of these substrates, as shown in the simulated JSC values listed in Table 1. FF is also simulated, showing FF improves with ITO thickness. Most importantly, a high FF of 74.9% is predicted on 100 nm ITO substrate, which has an extremely high resistivity caused by thermal treatment. This FF value is respectable compared with 1 cm2 devices reported in the literatures (Table S2).Table 1Simulated Photovoltaic Parameters of the Strip Device on ITO with Various ThicknessesThickness of ITO (nm)JSC (mA/cm2)VOC (mV)FF (%)RS (Ω cm2)PCE (%)10023.21,15074.95.219.915022.91,15076.14.720.120022.81,15076.84.520.125022.71,15077.14.620.230022.61,15077.44.520.135022.51,15077.54.520.0 Open table in a new tab If a VOC of 1,150 mV is assumed to be constant for all devices on different ITO substrates, PCE of around 20% is predicted for these devices, with PCE at its maximum when ITO thickness is at 250 nm before the optical losses in thickness ITO become dominating, reducing JSC and therefore PCE. To verify experimentally, strip devices were fabricated on these ITO substrates. The best and average PV parameters of these devices are provided in Table 2, the distributions of the PV parameters are plotted in Figure S7, and the best PCEs are plotted as a function of ITO thickness in Figure 5B to compare with the simulated values. It is worth noting that the FF of the demonstrated devices on thick ITO match the values simulated maintaining their values over 77%. However, there is a greater mismatch between demonstrated values and simulated values for devices on thinner ITO, possibly due to non-linearity in ITO conductivity with thickness. This explains the unexpected increase in RS for devices on thinner ITO compared with the simulated results. Interestingly, VOC is highest when ITO thickness is at its lowest, suggesting reasonable quality of the ITO film and that the interface can be formed even at such a thin thickness (100 nm). As predicted, devices show the best performance when ITO thickness is around 250 nm (Figure 5B), at which conductivity of the substrate is adequate (20 Ω/sq) and optical loss is adequately low (20%) for decent FF and JSC to be achieved. This results in a PCE of 20.3% with a JSC of 22.8 mA/cm2, a VOC of 1,149 mV, and an FF of 77.3%. The 300 nm ITO device also presents a decent PCE of over 20.1%, showing a lower JSC while compensated by a slightly higher FF of 77.6%. The results suggest that record-level FF and PCE can be achieved by a 1 cm2 device on high-resistivity substrates.Table 2Measured Best and Average (in Brackets) Photovoltaic Parameters of the Strip Devices on ITO with Various ThicknessesThickness of ITO (nm)JSC (mA/cm2)VOC (mV)FF (%)RS (Ω cm2)PCE (%)10023.2 (23.2 ± 0.1)1,161 (1,157 ± 9)72.3 (71.0 ± 1.0)5.9 (6.7 ± 0.7)19.5 (19.0 ± 0.3)15023.2 (22.9 ± 0.2)1,159 (1,149 ± 8)73.4 (72.1 ± 2.1)4.7 (5.6 ± 1.3)19.7 (19.0 ± 0.5)20023.0 (22.9 ± 0.1)1,149 (1,150 ± 5)75.5 (74.5 ± 0.8)4.4 (5.0 ± 0.5)19.9 (19.6 ± 0.3)25022.8 (22.8 ± 0.1)1,149 (1,153 ± 9)77.3 (76.0 ± 1.4)4.0 (4.8 ± 0.9)20.3 (20.0 ± 0.2)30022.7 (22.5 ± 0.2)1,145 (1148 ± 4)77.6 (77.1 ± 0.5)3.9 (4.4 ± 0.4)20.1 (19.9 ± 0.2)35022.4 (22.2 ± 0.2)1,150 (1,146 ± 7)77.4 (77.1 ± 0.8)4.0 (4.5 ± 0.6)19.9 (19.6 ± 0.2) Open table in a new tab The PCE of the devices can be further improved with the application of an antireflection layer such as MgF2, which raises JSC by 2%–4%. Figure 6A shows the J-V curve for one of the devices after the application of an antireflection layer, achieving a PCE of 20.6% under reverse scan (20.0% under forward scan). The steady-state efficiency of the champion device is also measured to be 20.5%, as shown in Figure 6B. The in-house-measured 20.04% efficient device was independently certified by Newport to be 19.63% efficient with an aperture area of 1.022 cm2 (see Figure S8). The JSC, VOC, and FF were independently measured to be 22.68 mA/cm2, 1.15 V, and 75.8% respectively. This is among the highest certified PCEs for devices with an area larger than 1 cm2 to the best of our knowledge and is the highest for a 1 cm2 device fabricated on a low-conductivity substrate (20 Ω/sq). This is also the highest for 1 cm2 certified device fabricated by the gas-quenching method. Another advantage of this work is that the modeling methods (optical analysis for TCO optimization, 2D finite element analysis to determine impact of RS, and diode models for determining electrical characteristics) and the design principles presented in this work are useful for optimizing transparent conductive oxide thickness and cell dimensions in modules. Where cells are inter-connected in series and as cell isolation and cell interconnection processes continue to improve, reducing dead area loss, cells in the shape of long strips can be made narrower allowing more resistive (higher than the typical 7 Ω/sq or 15 Ω/sq used in small device demonstration work) and therefore more transparent TCO substrates boosting module performance further. In conclusion, high-efficiency 1 cm2 mesoscopic PSCs have been successfully demonstrated on high-transparency, low-conductivity ITO substrates by employing a new electrode wrap-around design that dramatically improved the FF of the devices even on ITO that became less conductive after annealing at high temperature. Cell geometry was further optimized, guided by simulation. By using the strip device design, FA0.80MA0.15Cs0.05PbI2.85Br0.15 PSCs fabricated on high-temperature annealed low-conductivity ITO substrate achieved a high PCE exceeding FTO-based devices. The optical and electrical properties of in-house deposited ITO were characterized to examine the effect of ITO thickness on substrate performance. It was found that FF improves with ITO thickness up to 250 nm, while the JSC follows an opposite trend. When ITO thickness is at 250 nm, the conductivity of the substrate is adequate (20 Ω/sq) and optical loss is sufficiently low (20%) for decent FF and JSC to be achieved. The corresponding strip device with a geometry of 4 × 25 mm2 achieved a certified PCE of 19.63%, which is among the highest certified devices with aperture area greater than 1 cm2. This is the highest for cells fabricated on high-resistive substrates (20 Ω/sq) and also the highest for a 1 cm2 certified device fabricated by the gas-quenching method. The new cell geometry, wrap-around metal electrode design, and simulation methods reported in this work expand the substrate choices for current and future high-efficiency, large-area perovskite devices and modules.