Abstract
A substantial improvement in the electrochemical capacitance-voltage (eCV) profiling technique is proposed by effectively reducing the diode area, thereby extending the range of applicability of this technique to highly spatially confined carrier systems and heterostructures. This modified technique makes use of the dielectric properties of photoresist films into which small area holes can be defined by standard photo- lithographic techniques. It is easily implemented in a commercially available system and excellent quality data across silicon (Si)/silicon-germanium (SiGe) two-dimensional electron gas (2DEG) heterostructures and delta- (-) doped gallium arsenide (GaAs) layers are obtained reproducibly. Applying this technique to modulation-doped field-effect transistors (MODFETs) it is possible to clearly identify the supply, spacer and channel layers in such structures; corresponding measured sheet densities exhibit excellent agreement with those determined by other techniques. The proposed modifications raise the eCV technique to a valuable complementary assessment tool in the determination of room temperature transport properties of heterostructures with device layer design.
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