Abstract
The hot spot onset in power bipolar transistors is examined, both from the experimental and simulation viewpoint. A simple three-dimensional electro-thermal model is proposed, including an accurate description of the layout structure, a fitting of the experimental dependence of input and output characteristics from the temperature, and packaging and heatsink thermal modelling. Experimental detection of transient temperature maps, by means of the infrared detection technique, validate the model results about the hot spot onset and location for two commercial power BJTs. Collector current crowding is also described by the model in the hot spot mode. Finally, a detailed analysis of the hot spot onset locus in the I c− V cc plane is performed, showing a good agreement between experimental and simulation data.
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