Abstract

Herein, we fabricated CdSe-based thin-film transistors (TFTs) employing two different hybrid dielectric gates, SiO2–poly(vinylphenol) and Al2O3–3-glycidoxypropyltrimethoxysilane–polymethylmethacrylate. These organic–inorganic hybrid dielectric layers were processed by the sol-gel method at low temperatures (<200 °C), and the CdSe semiconductor layer was deposited by R.F sputtering at room temperature. The chemical and physical properties of the hybrid thin films were thoroughly evaluated by Fourier transform infrared spectroscopy, field emission scanning electron microscope, atomic force microscopy and surface energy analysis. The results have shown an adequate interaction between both organic and inorganic phases in the hybrid material and the obtained hybrid thin films are very homogeneous with low surface roughness. Further, the dielectric properties of these hybrid thin films showed salient features with similar leakage currents for both dielectrics of the order of 10−6 A cm−2, and dielectric constants of 7 and 11 at 1 kHz for the silica and alumina based dielectrics, respectively. The higher dielectric constant of the alumina hybrid dielectric is associated to excessive oxygen defects such as hydroxyl groups (OH) and oxygen vacancies (Vo), which produce high dielectric loss through hopping relaxation. To investigate the feasibility of these two hybrids as dielectric gate layers we constructed TFTs with CdSe as active channel layer. Among these, TFTs fabricated with silica hybrid dielectric showed the best performance with a current off/on ratio of 104, threshold voltage of 1.1 V and mobility of 22.2 cm2 V−1 s−1. Meanwhile, the TFT device with alumina hybrid as dielectric gate layer exhibited a diminished electrical performance in terms of lower mobilities, which is mostly related to the defects at the dielectric/semiconductor interface. These defects manifested as well in the capacitance measurements of the alumina hybrid dielectric and have a strong influence on the device mobility since the charge carriers traps restrict the electrical transport in the semiconductor channel.

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