Electrical properties of the p+-gate electrode of an a-Si/poly-Si double layer

Abstract

The single and mixed p+-gate electrodes of a-Si and poly-Si layers were fabricated and analyzed by cross-sectional transmission electron microscopy, Raman, X-ray diffraction, secondary ion mass spectrometry and electrical measurements. The as-deposited a-Si layer, which transformed to a large grain polycrystalline structure during annealing, showed lower resistivity and less gate electrode-induced strain than the single poly-Si layer. The interface in the mixed layer of a-Si and poly-Si layers showed a discontinuity of grains of upper and lower layers. The mixed electrode layers on 80 Å thick N2O oxide were implanted with BF2+ at 30 keV and annealed at 900 °C to fabricate p+-gate MIS capacitors. The high frequency and quasi-static C-V measurements of the MIS capacitors showed the formation of a shallow p+-n junction in the Si substrate of MIS capacitors, caused by B and F atoms penetrating into the Si substrate through the ultrathin N2O gate oxide during annealing. However, the mixed layer including the a-Si layer partially restricted B penetration into the Si substrate during furnace annealing, and thus MIS capacitors with the mixed layer had better electrical properties, such as time dependent dielectric breakdown and charge trapping, than those with the single poly-Si electrode structure. This might be due to less B penetration into the oxide layer and relaxation of residual stress in gate electrodes owing to phase transformation of a-Si to poly-Si.