Electrical properties of Pt/SrBi2Ta2O9/Bi4Ti3O12/p-Si heterostructure prepared by sol-gel processing

Abstract

Low-temperature processing as low as 550–700 °C of Pt/SrBi2Ta2O9 (SBT)/Bi4Ti3O12 (BIT)/p-Si heterostructure has been performed by a sol-gel method. The effects of annealing temperature on current density, C-V characteristics, and memory windows of Pt/SBT/BIT/p-Si heterostructure were investigated. The SBT/BIT multilayer films were polycrystalline with no pyrochlore phase and no preferred orientation. The leakage current density was under 3 × 10−7 A/cm2 at 5 V with asymmetry hysteresis loops for Pt/SBT/BIT/p-Si heterostructure. Although all C-V curves showed clockwise ferroelectric hysteresis loops and the memory window reached a maximum of 0.78 V at a sweep voltage of 5 V, the memory window changed asymmetrically with the variation of annealing temperature and sweep voltage. The maximum memory window of Pt/SBT/BIT/p-Si heterostructure prepared at lower temperatures was narrower at lower sweep voltage. The asymmetric behavior of the C-V characteristics was discussed in terms of electron injection from Si and the ferroelectric polarization effect.