Electrical properties of high density arrays of silicon nanowire field effect transistors

Abstract

Proximity effect corrected e-beam lithography of hydrogen silsesquioxane on silicon on insulator was used to fabricate multi-channel silicon nanowire field-effect transistors (SiNW FETs). Arrays of 15-channels with a line width of 18 nm and pitch as small as 50 nm, the smallest reported for electrically functional devices, were fabricated. These high density arrays were back-gated by the substrate and allowed for investigation of the effects of scaling on the electrical performance of this multi-channel SiNW FET. It was revealed that the drain current and the transconductance (gm) are both reduced with decreasing pitch size. The drain induced barrier lowering and the threshold voltage (Vth) are also decreased, whereas the subthreshold swing (S) is increased. The results are in agreement with our simulations of the electric potential profile of the devices. The study contains valuable information on SiNW FET integration and scaling for future devices.