Abstract
Advanced Surface Laminar Circuit (Adv-SLC) is a build-up substrate technology designed to satisfy the requirement of the most advanced semiconductor chips. Adv-SLC is featuring a low Coefficient of Thermal Expansion (CTE) of 10 ppm/degC that reduces the strain in the solder joints and Cu/low-k stacked structure of semiconductor chips during the reflow process, ensures the solder joint reliability, and protects internal delamination of the Cu/low-k stacked structure. This paper describes the power integrity and signal integrity of Adv-SLC and the capability to reduce total layer count with considering X-talk, to reduce package size, and to improve Power Integrity by using Adv-SLC.
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