Abstract

The interfacial electrical properties of deposited oxide (SiO2) onto cubic silicon carbide (3C-SiC) were investigated after different post-oxide deposition annealing (PDA) by means of metal–oxide–semiconductor (MOS) capacitors and nanoscale capacitance mapping. The deposited oxides subjected to PDA at 450 °C in either nitrogen or forming gas showed a reduction of the interface and oxide traps, as well as an improved oxide field strength compared to the thermally grown insulating layer. Spatially resolved nanoscale capacitance mapping performed onto the oxide surface revealed that the density of the electrically active stacking faults (SFs) in 3C-SiC is diminished by appropriate PDA. The results pave the way to obtain an ideal SiO2/3C-SiC system suitable for power device applications.

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call

Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.