Abstract
We propose the power-to-failure vs. time-to-failure relationship (power profile) as a measure to determine the EOS hardness of integrated circuits. Bipolar integrated circuits with different I/O ESD protection designs were characterized for HBM-ESD and EOS under unipolar stress conditions. Measured power profiles indicate that good ESD performance is not a sufficient condition to assure EOS robustness. Furthermore, experimentally measured power profiles together with failure analysis techniques can pinpoint layout design weaknesses.
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