Electrical overstress due to ESD induced displacement currents

Abstract

In this paper a new failure mode is introduced, which is related to the large d V/d t of ESD pulses. It was observed after +4 kV HBM stress for a 90V-BCD technology device and resulted in a gate oxide defect of a low voltage PMOS transistor, which was hidden deeper in the IC's circuitry. The underlying failure mechanisms are discussed based on experimental and simulational findings and measures for early identification and protection of potentially sensible devices are proposed.