Electrical Network Functions of Common-Ground Uniform PassiveRLCLadders and Their Elmore’s Delay and Rise Times

D B Kandić,B D Reljin,I S Reljin

doi:10.1155/2013/691740

Abstract

In the paper are presented the expressions for all network functions of common-ground, uniform passive ladders having, in general, complex terminations at both their ends. The Elmore's delay and rise times calculated for selected types ofRLCladders have indicated their slight deviation from delay and rise times obtained according to their classical definitions. For common-ground, integrating typeRCladder with voltage-step input, the Elmore's delay- and rise-times are produced in closed-form, both for ladder nodes and points. Furthermore, it is proposed a particular common-ground, uniformRLCladder being amenable to application as delay line for pulsed and analog input signals. For this ladder, the Elmore's delay and rise times relating to their node voltages are produced in a closed-form, enabling thus with the realization of artificial (a) pulse delay line with arbitrarily and independently specified overall Elmore's delay and rise times and (b) true delay line with arbitrarily specified delay time for frequency bounded analog and/or pulsed input signals. In cases (a) and (b), precise procedures are formulated for calculation of ladder length and of all itsRLCparameters. The obtained results are illustrated with several practical examples and are, also, verified throughpspicesimulation.

Highlights

Modeling of digital MOS circuits by RC networks has become a well-accepted practice for estimating delays [1,2,3,4,5,6]
Simple closedform bounds for signal propagation delay in linear RC tree models for MOS interconnections derived in [3] are, valid for the more general class of linear networks known as RC meshes, which are useful as models for portions of MOS logic circuits that cannot be represented as RC trees [6]
The obtained results are simplified for ladders with seven specific pairs of complex double terminations

Summary

Introduction

Modeling of digital MOS circuits by RC networks has become a well-accepted practice for estimating delays [1,2,3,4,5,6]. For the integrating type of distributed RC impedance, common-ground ladder as a model of two-wire line, it has been suggested that it might be used as a true pulse delay line [13], provided that, Schmitt triggers are used for reshaping the delayed and edge-distorted transmitted signals This type of delay line with step-input excitation has already been thoroughly investigated in [14]—where Elmore’s delay time is given in closed form only for ladder nodes, and for Elmore’s rise time is offered a conjecture relating to its lower bound for overall network. All the initial conditions associated to the network reactive (LC) elements are assumed to be zero

Section 1

Findings

Conclusions