Abstract
The astonishing evolution in microelectronic systems pushes the conventional 2D technology to its ultimate limits in terms of both performance and functionality while reducing power and cost criteria. To overcome such challenges, using 3D integration with Through Silicon Vias (TSVs) interconnects, seems to be as a good candidate for the assembly of multilayers into a single stack. Therefore, in this work, we report on the evaluation of the impact of TSV interconnects on the electrical performance of CMOS circuits, particularly the CMOS ring oscillator, by means of SPICE-like simulations. To this purpose, an analytical model is used, which is able to describe the behavior of TSVs and ring oscillator in a circuit level and other phenomena such as the substrate coupling. This study is made in order to optimize the performance of a ring oscillator with the presence of 3D-TSV interconnects as a function of different technological parameters. The analytical approach has proved its effectiveness to perform rapid and reliable simulations to investigate the substrate coupling induced by the TSV on a commonly used CMOS circuits such as the ring oscillator.
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