Electrical Modeling of the Effect of Photoelectric Laser Fault Injection on Bulk CMOS Design

Abstract

Abstract Fault injection from infrared laser is a common practice among Information Technology Security Evaluation Facility (ITSEF) labs for testing CMOS circuits, and obtained effects are very versatile. However, from our point of view, the details of the phenomenona that occur in the integrated circuit have yet to be investigated. The common hypothesis is that the photoelectric current created during the light stimulation flows through the P-N junctions, and corrupts voltage outputs of the cells. In this paper, we consider the vertical parasitic bipolar junction transistors inherent to CMOS bulk devices. We show that these parasitic transistors contribute to the injected fault at a higher rate than just the P-N junctions of the OFF MOS side. There are two features of such results. First, the space charge region of the N-well / P-substrate junction is wide and will induce a stronger photocurrent. Second, this current will be amplified by the parasitic bipolar transistor and thus lead to more effects. These results are obtained by electrical simulations on a CMOS inverter. The size of the laser spot is taken into account via neighboring cells that are also illuminated. To induce an effect, small spot size needs a very high-power density, which is not always achievable. Increasing the illuminated area to inject more power is then a solution; simulations illustrate this point.