Electrical Interconnection and Bonding by Nano-Locking.

Jielin Guo,Yu-Chou Shih,Frank G Shi

doi:10.3390/nano11061589

Jielin Guo, Yu-Chou Shih + Show 1 more

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https://doi.org/10.3390/nano11061589

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Abstract

The growing demand for increased chip performance and stable reliability calls for the development of novel off-chip interconnection and bonding methods that can process good electrical, thermal, and mechanical performance simultaneously as well as superior reliability. A chip bonding method with the concept of “nano-locking” (NL) is proposed: the two surfaces are locked together for electrical interconnection, and the connection is stabilized by a dielectric adhesive filled into nanoscale valleys on the interconnecting surfaces. The general applicability of this new method was investigated by applying the method to the die-substrate bonding of two different packages from two different manufacturers. Electrical, optical, and thermal performances as well as reliability tests were carried out. The surface morphology of the bonding package substrates plays an important role in determining the contact resistance at the bonding interfaces. It was shown that samples with different roughness height distribution on the metallic surfaces formed a different total number of contacts and the contact area between the two bonding surfaces under the same bond-line thickness (BLT): a larger number of contact area resulted in a reduced electrical resistance, and thus an improved overall device performance and reliability.

Highlights

To better solve the challenges above-mentioned, an innovative die-substrate bonding method is proposed with a concept of “nano-locking” (NL): the two surfaces are locked together for electrical interconnection, and the connection is stabilized by a dielectric adhesive filled into nanoscale valleys on the interconnecting surfaces
This study focused on the influence on the contact resistance brought by different surface morphologies on the metallic pads
The surface morphology plays an important role in determining the real contact area, which in turn will lead to an effect on the transmission of electric current and heat across the contact interface

Summary

Introduction

A typical chip-to-package electrical interconnect/bonding often utilizes electrically conductive die attach adhesives (DAAs), die attach films (DAFs), or solders to secure a reliable thermal and electrical conduction path between the chip and substrate [2]. For a typical chip-to-package electrical bonding using a liquid DAA to be reliable, its bond-line thickness (BLT) is often required to be as thick as over 25 μm, while the newly developed DAF can reduce the BLT to as thin as 10 μm. For chip-to-package electrical interconnections using a solder, a typical BLT thickness of the order of 30 μm is required to avoid thermo-mechanical reliability problems [3]. The interconnection and bonding technologies have become the bottleneck to achieving high integration density while keeping the enhanced device performance and high yield [4].

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