Electrical Instability Suppression in 4H-SiC Power MESFETs

Abstract

ABSTRACTSiC has attracted great interest for high power microwave applications because of its superior intrinsic properties compared to Si and GaAs. Steady demonstrations of increasingly higher power handling capability have been achieved in recent years. However, SiC MESFETs still suffer from significant drain current degradation under RF operation or long-term DC stress. This degradation can be recovered after long periods of relaxation or immediately by illumination under UV light, which is indicative of a trapping effect. The origin of this effect has been attributed to either electron trapping at the device surface between the gate and drain or trapping at the epi-substrate interface due to the presence of electrically active contaminants in the bulk. Newly available “high purity” (non-vanadium compensated) bulk 4H semi-insulating SiC substrates were used in an effort to limit the effect of V-related deep level trapping at the substrate/epilayer interface. To investigate the effect of V on SiC MESFET performance, we compare similar devices fabricated on V compensated, and “high-purity” 4H-SiC substrates without intentional V doping. Presence or absence of V is confirmed by secondary ion mass spectrometry (SIMS) analysis. Pulsed I-V measurements as well as current- and capacitance-based deep level transient spectroscopy (DLTS) measurements were performed to assess trapping activation energy and density. An assessment of device performance and stability for each substrate type is made using RF load-pull measurements and device long-term DC bias stressing at temperature.