Electrical Impedance Tomography System Based on Time Interleaved Analog to Digital Converter

Abstract

This paper proposes a method to improve the signal-to-noise ratio (SNR) of electrical impedance tomography (EIT) system by increasing the bits of Analog-to-digital converter (ADC). To balance the SNR and data acquisition rate, time interleaved analog to digital converter (TIADC) technique is innovatively applied. In the TIADC unit, an array of M analog-to-digital converters (ADCs) operates in a parallel round-robin manner, which enables a higher sampling rate. With the TIADC-based EIT system, the frequency constrains are derived. When the frequencies of boundary voltage meet the frequency constrains, the TIADC employed in EIT system can be treated as an ideal one. The integral effect of digital matched filter makes the impacts of mismatches of TIADC ignored. Beyond the proposed frequency constrains, the impact of mismatches would occur and the SNR would be lowered. To tackle with this issue and expand the frequency range of boundary voltages in TIADC-based EIT system, a computationally-efficient mismatch calibration algorithm is also proposed. Experiments were conducted in a laboratory-built EIT system, which demonstrate that a significant SNR improvement can be achieved by employing the TIADC structure. It can be concluded that the TIADC is a promising candidate of ADC when high SNR is required in an EIT system.