Abstract

An understanding of the effects of dislocations in HgCdTe diodes is complicated by several issues such as the diode architecture, diode formation process, and the thermal history and location of the dislocations. To help decouple the effects of these factors, high stress films were used to lithographically introduce dislocations with different densities and locations during the fabrication process of ion implanted, n-on-p diodes. Both array and diode test structures were studied. After fabrication, the diodes were characterized with variable temperature I–V measurements and noise measurements. The diodes were then stripped and defect etched to quantify the density and distribution of the dislocations. The effects of these process-induced dislocations were analyzed and compared to the effects of as grown dislocations, subgrain boundaries and dislocations in other device architectures reported in the literature.1,2 In general, high densities of either as grown or process-induced dislocations in n-on-p, ion implanted diodes severely degrade device performance by producing field dependent dark current At 77K, dislocation densities greater than the mid 106 cm−2 can produce dark current densities in excess of the diode diffusion current. Dislocations located near the outer periphery of the diode produce approximately ten times the dark current of interior dislocations. Grain boundaries, sub-grain boundaries, and twins also produce sufficient field dependent dark current to limit diode performance at 77K. The dark current produced by dislocations is nearly temperature in dependent, suggesting rather severe limitations on dislocation densities for low temperature diode operation.

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