Abstract

Wiring rules are required for high-speed logic circuits. They ensure proper operation of the receivers connected at any point on the transmission lines, and they guarantee the integrity of the delay equations used to predict the system performance. These wiring rules are strongly dependent on the driver characteristics and the system design requirements. It is important to develop a rule for maximum stub length to avoid excessive oscillations and long decaying time constants on the main line, which compromise system performance. The algorithms and procedures outlined greatly facilitate the developing of net delay equations for a high-speed package technology with various net types without sacrificing accuracy. The fundamental tradeoffs between the wiring rules, the signal quality, the number of delay equations, and the magnitude of their approximation error are discussed. >

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