Electrical current induced local thermal stress caused on stacked 3D-ICs

Abstract

For the feature of "slim and light" in portable devices, stacked 3D-IC architecture was introduced in the advanced packaging techniques. The traditional FR-4 substrate was substituted by Si substrates. In general, the thickness of Si chip and substrates would be larger than 300 micron. However, silicon is rigid and has high resistance of deformation. Therefore, the thermal stress caused by the thermal expansion mismatch between Si chip, underfill and FR-4 substrate are less important due to both the chip and substrate side are rigid silicon. However, for future applications, silicon at chip and substrate sides should be thinned. The reliability issues caused by the stress become a serious issue. Furthermore, with increasing current density in the Si chip, the local heating caused by Joule heat becomes critical. In this study, thin 3D stacked chips stressed with the current density of 1×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">4</sup> A/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> were investigated at different temperatures by using in-situ synchrotron radiation X-ray diffraction method. Owing to high resolution of synchrotron radiation X-ray, the results showed that the local heating caused by the electrical current is obvious; it affects the stress distribution in the chips. At different temperatures, the effects become complex and the properties of underfill could seriously affect the stress state in the chips.