Electrical Coupling Effect of Forksheet FET for Power, Performance, and Area Analysis

Abstract

We analyze the electrical coupling effect of a fork-shaped field-effect transistor (FSFET) and compare FSFET and the nanosheet FET (NSFET) in terms of logic cell power, performance, and area. FSFET enables excellent scaling and is a promising candidate to replace NSFET at the sub 3-nm node. However, FSFETs are vulnerable to electrical coupling because n/p-type FETs (N/PFETs) are close to each other with the dielectric wall in the middle. This electrical coupling causes threshold voltage shift and increases in subthreshold slope, ON-current, and drain-induced barrier lowering (DIBL). Since the gate bias of the adjacent device has a greater effect than the source and drain, the coupling effect occurs more when the gates of N/PFETs are split. Our results show that small wall, small channel width, and high wall permittivity cause a significant electrical coupling in a sub 3-nm node. Coupling within the criteria can be secured for an FSFET with a 15-nm channel width by applying a 17-nm SiO2 wall. With these coupling guidelines, the FSFET logic cell shows up to 21% improvement in an area compared to NSFET at the 15-nm channel width. Compared with NSFET, the FSFET shows an almost similar performance at the same power; in this case, the area improves by 15.5%–16.4%. Overall, FSFET should be designed to improve the electrical coupling, and FSFET can achieve almost the same power and performance as NSFET in a small area.