Electrical characterization of trapping phenomena at SiO2 /SiC and SiO2 /GaN in MOS-based devices

Abstract

In this paper, some aspects of the electrical characterization of trapping phenomena occurring at interfaces between insulators and wide band semiconductors (WBG) are presented, with a focus on the SiO2/SiC and SiO2/GaN systems. In particular, time resolved capacitance, current measurements, and parallel conductance measurements as a function of frequency were correlated to investigate trapping states in SiC and GaN MOS-structures, allowing to distinguish between slow and fast states in these systems. Furthermore, gate current measurements enabled us to get insights into the near interface traps (NITs) present inside the SiO2 layer. Evidently, in these systems, although post-oxide deposition annealing treatments can reduce the interface traps (down to the 1011–1012 cm−2 eV−1 range), the presence of the NITs is responsible for an anomalous behavior of the current conduction, penalizing the threshold voltage stability. Time-dependent current and conductance measurements, performed in appropriate bias ranges, enabled to determine the density of NITs (1 × 1011 cm−2). The impact of the observed trapping phenomena on the SiO2/SiC(GaN) transistor operation is briefly discussed.