Abstract
As semiconductor digital logic and analog I/O bandwidth operates close to 10Gbps ranges, semiconductor package technology requires much tighter attenuation and timing budgets. To overcome electrical performance degradation while maintain cost-performance BOM models, it is required to consider the effect of PBGA package substrate Cu plating bars. In this paper, we analyzed the electrical performance based on the effect of Cu plating bars.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
