Abstract
This paper confirms that the electrical characteristics of FinFETs such as the on/off ratio, drain-induced barrier lowering (DIBL), and sub-threshold slope (SS) can be improved by optimizing the FinFET spacer structure. An operating voltage that can maintain a life of 10 years or more when hot-carrier injection is extracted. An excellent on/off ratio (7.73×107) and the best SS value were found at 64.29 mV/dec with a spacer length of 90 nm. Under hot carrier-injection conditions, the supply voltages that meet the 10-year lifetime condition are 1.11 V, 1.18 V, and 1.32 V for spacer lengths of 40 nm, 80 nm, and 120 nm, respectively. This experiment confirmed that, even at low drain voltages, the shorter is the spacer length, the greater is the deterioration. However, this increasing maximum operating voltage is very small when compared to the increase in the driving voltage required to achieve similar performance when the spacer length is increased; therefore, the effective life is expected to decrease. The results indicate that structural optimization must be performed to increase the driving current of the FinFET and prevent degradation of the analog performance.
Highlights
The performance of semiconductors is improved by scaling the gate length up to 10–15 nm [1,2,3].as the distance between source and drain regions decreases, the electric field in the channel increases, while the ability of the gate to control the channel region decreases
The FinFET structure reduces the occurrence of gate-oxide traps and gate critical paths, owing to the reduction of the hot-carrier effect caused by lightly-doped drain (LDD)
We present a bulk-Si N-channel FinFET device that has desirable transistor characteristics and competitive short-channel performance
Summary
The performance of semiconductors is improved by scaling the gate length up to 10–15 nm [1,2,3]. As the distance between source and drain regions decreases, the electric field in the channel increases, while the ability of the gate to control the channel region decreases This is known as “short channel effect (SCE)”. Multi-gate FinFETs were introduced to reduce the leakage current and improve the gate controllability of the transistor channel. The effective channel length is larger than the physical gate length due to the undoped spacer regions. While the introduction of spacer improves the short-channel performance of the devices, drive current is reduced due to higher series resistance in the spacer regions. We present a bulk-Si N-channel FinFET device (bulk N-FinFET) that has desirable transistor characteristics and competitive short-channel performance. The device design parameters of the width (Wfin ), transistor length (L), and spacer length (LSD). Using the Ids–Vgs graph for changes in the spacer length
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