Electrical characteristics of Au/PVP/n-Si structures using admittance measurements between 1 and 500 kHz

Abstract

In this study, Au/n-Si structures with PVP polymer interlayer were fabricated and characterized using capacitance/conductance–voltage–frequency (C/G–V–f) measurements. Obtained electrical parameters were found to be sensitive to frequency due to polymer interlayer, changes of traps/states (Dit/Nss) level, interfacial/dipole polarization. The dispersion in C and G in depletion region is due to Nss/polarization, while the dispersion in accumulation region is due to interlayer/series resistance (Rs). The voltage-dependent profiles of Nss and Rs were derived using the methods of low–high frequency capacitance/Hill-Coleman and Nicollian–Brews, respectively. The width of depletion layer (Wd) and barrier height (ΦB) values increase with increasing frequency almost linearly. On the other hand, Rs decreases with increasing frequency whereas the maximum electric field (Em) exhibits opposite behavior. The high frequency C/G–V plots were corrected to reveal the Rs effect on them. The experimental results indicate that the growth of PVP interlayer by spin coating at the Au/n-Si interface yields a preferable and suitable device compared to devices with conventional insulating interlayer due to some advantages of polymer interlayers such as low-cost/weight, flexibility, and easy grown processes.