Abstract
The electrical behaviour of porous silicon layers has been investigated on one side of p-type silicon with various anodization currents, electrolytes, and times. Electron microscopy reveals the evolution of porous silicon layer morphology with variation in anodization time. In this work electrical conductivity of bulk silicon and porous layer which is formed by electrochemical etching is compared due to I V measurements and calculation of activation energy. We have also studied the dependence of porous silicon conductivity on fabrication conditions. Also the e ect of the temperature on conduction of porous silicon at di erent frequencies is investigated. At last dependence of capacitance on the temperature was probed at 10 10 Hz frequency range. PACS: 73.30.+y, 73.40.Sx, 73.50.−h, 73.90.+f, 73.63.Rt, 68.37.Hk
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