Electrical and physical characterization of high-k dielectric layers

Abstract

The continuous reduction of the gate insulator (SiO/sub 2/) layer thickness in advanced complementary metal-oxide-semiconductor (MOS) devices leads to excessive gate leakage currents and device reliability problems. Consequently, alternative gate insulators with higher electrical permittivity than SiO/sub 2/ are currently widely investigated for the future generations of MOS transistors. The use of dielectric layers with higher electrical permittivity should allow us to use thicker films with electrical thickness equivalent to ultra-thin SiO/sub 2/ (as far as gate capacitance is concerned), and one would thus expect to reduce the leakage current and improve the reliability of the gate dielectric layer. In this paper, we investigate the electrical properties of MOS capacitors with ultra-thin high permittivity gate stacks consisting of an ultra-thin interfacial oxynitride (SiON) layer and a metal oxide layer. The frequency dispersion in the capacitance-voltage characteristics is first studied. Next, the polarity dependence of the current through the gate stack is addressed. Finally, the generation of traps during constant gate voltage stress of capacitors is investigated.