Abstract
3-D medical ultrasound imaging enables new diagnostic possibilities and modalities. In a computational process called beamforming, a 3-D volume is reconstructed from several thousands of analog signals. Today’s systems rely on massive analog preprocessing to reduce the computational burden of the subsequent digital processing system. In this paper, we present a configurable beamformer (BF) architecture, which demonstrates for the first time that it is possible to implement the entire 3-D delay and sum beamforming fully digitally and on one single chip, without requiring the off-chip memories. We present a presilicon implementation of a single-chip BF in an advanced 28-nm silicon-on-insulator technology. The BF targets a fully sampled 10k element 8-MHz bandwidth transducer head and is able to produce 298.1M focal points (FPs) per second—enough to produce a high-resolution volume with 16.3MFP at 15 Hz. All delays are computed online and on-chip to eliminate the power-hungry external memories for delay storage. The final design (register-transfer-level and floorplan) has a complexity of 342M gate equivalents requiring 1.68cm2 of area. The core power is estimated to be 30.3 W, resulting in an unprecedented power efficiency of 98.4G beamforming operations per watt.
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More From: IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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