Abstract
To enable the continued scaling of distributed storage, failure recovery schemes that have low latency and low redundancy are indispensable. Minimum storage regenerating (MSR) codes have been developed to achieve this goal. Compared to other MSR codes, the recent coupled-layered (Clay) codes have many advantages such as low sub-packetization level, small finite field for construction, and uniform repair bandwidth over data and parities. This brief proposes efficient VLSI architectures for Clay encoder and decoder. Through exploiting subfield elements of finite fields, the logic complexity is substantially lowered. Additionally, the buffer size is reduced by optimizing the coupling scheme. For an example Clay code with $(n,k)=(6,4)$ , the proposed designs achieve 12% and 24% logic complexity reduction on the encoder and decoder, respectively, under the same timing constraint.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: IEEE Transactions on Circuits and Systems II: Express Briefs
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
