Efficient VLSI Architecture for Residue to Binary Converter

Abstract

Residue number system (RNS) is a very useful technique to improve speed and arithmetic accuracy of digital signal processing implementations. It is based on the decomposition of a number represented by a large number of bits into reduced word length residual numbers. These residual arithmetic blocks are independent of each other. Consequently, this approach reduces the carry propagation delay and hence, speeds up the overall system. This fact makes RNS an interesting method for a low level parallelization. In addition, modular operation with high computational cost, as for example multiplication, can be speeded-up by using suitable isomorphisms stored in look-up tables. RNS binary conversion is a critical operation for the implementation of modular processors. The choice of moduli is strictly related to the performance of this converter and affects the processor complexity. This chapter presents a conversion method based on a class of coprime moduli. The method and the related architecture can be easily extended to a large number of moduli. In this way the magnitude of the modular arithmetic's used in the RNS system can be reduced. The proposed method allows the implementation of very fast and low complexity architectures. The main drawback for the use of RNS in high speed DSP is related to the conversion between the internal and the external number representations. This conversion requires the translation from binary to RNS and vice versa and uses two different types of converters: (1) The input converter to transform binary numbers into a set of numbers corresponding to the RNS representation and (2) The output converter for the inverse conversion and to transform the numbers from RNS to binary.