Efficient VLSI Architecture for ECG Data Compression

Abstract

This paper presents an efficient ECG signals compression techniques using a 2D DWT coefficient thresholding and its design implementation of an efficient JPEG2000 encoder that employs the Distributed Arithmetic (DA) technique for the complex computation of Discrete Wavelet Transform (DWT).2D approaches exploit the fact that redundancy of ECG signal occurs between adjacent beats and adjacent samples. Cut and aligned error signal to form 2D matrix, then 2D matrix is transformed. Ultimately wavelet coefficients are segmented into groups and thresholded. DA-DWT is used for reducing the complex computations, which can increase the speed and throughput as well. Architecture is based on the principles of pipelining and parallelism to obtain the optimal speed and throughput. Architecture is simple, modular and cascadable for computing a DA-DWT. This technique is faster when ROM table in on chip memory and memory size is reduced by splitting ROM table .The description and functionalities of the design is modeled by Verilog HDL. The simulation and synthesis methodology are used to target it on Virtex-II Pro FPGA (xc4v1x25-12sf363) that consumes 6% resources of FPGA and shows the clock frequency 310.207 MHz by DADWT using Sym20. Experiments on selected records from MIT-BIH arrhythmia database revealed that the proposed design is significantly more efficient.