Efficient Verification Methodologies for Digital IPs in VLSI Design: A Comparative Study and Analysis

Abstract

Abstract: Verification of digital IPs in VLSI is an essential step in the design and development of integrated circuits. With the growing complexity of digital systems, the verification process has become increasingly challenging and time-consuming. This survey paper provides an overview of various verification methodologies used in the verification of digital IPs in VLSI. The paper focuses on the design and verification of IP cores using different verification methodologies, assertion-based reconfigurable testbenches, UVM-based testbench architecture for coverage-driven functional verification, practical and efficient SOC verification flow by reusing IP testcase and testbench, IP reusable design methodology, development of verification environment for SPI master interface using SystemVerilog, design of UART using Verilog and verifying using UVM, UVM-based Controller Area Network Verification IP (VIP), UVM-based verification of a mixed-signal design using SystemVerilog, SoC level verification using SystemVerilog, and function verification of SRAM controller based on UVM. The survey paper also describes the complexity of the problem, major approaches, challenges in the domain, history of development of the topic, comparison of various approaches, and the best approach for verification of digital IPs in VLSI.