Efficient Threshold Architectures with Bounded Fan-Ins for Exclusive-ORs

Abstract

As process technologies scale into nanometer region, new opportunities as well as challenges arise. Some emerging nanotechnology devices that are promising candidates to replace the CMOS technology are particularly suitable for threshold logic implementations. While most conventional Boolean gates, including AND, OR, NOT, NAND, and NOR, can be implemented by a single threshold gate, exclusive-OR (XOR) is an important exception. This represents a significant obstacle, since XORs are essential building blocks for all finite field arithmetic operations over GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> ), which in turn are used in various applications. In this paper, we propose efficient architectures with finite fan-ins for XORs based on threshold gates, and our architectures greatly outperform architectures obtained by first expressing an XOR based on other Boolean gates and then using their threshold logic implementations. Our work in this paper is novel in two aspects. First, in addition to two-input XORs, we also investigate multi-input XORs, because they are suitable for threshold logic implementation and are very instrumental in finite field arithmetic operations. Second, our architectures differ from previous implementations of XORs based on threshold logic in that our architectures assume bounded fan-in, which is critical to the reliability to nanotechnology devices.