Efficient ternary comparator on CMOS technology

Abstract

Binary (base-2) comparators suffer from interconnect-complexity and associated power-delay, area, fan-in/out, reliability and parasitic-overhead. Ternary (base-3) counterparts can effectively reduce interconnect complexity due to more-data-carrying capability and hence aforesaid drawbacks. A new idea to compare 2-ternary-inputs is proposed using Double-Pass-Transistor-Logic realized on Normal-Process-Enhancement-type-MOS (NPEMOS-technology) without threshold modification. The design-strategy is first presented for 1-trit ternary-comparator, extended next to compare two n-trit ternary-inputs. A 4-trit ternary-comparator is designed to demonstrate the proposed idea and to evaluate and benchmark performance. Proposed design is optimized using BSIM4 device-model on 32 ​nm-CMOS-technology on 1.0V supply-rail at 27 ​°C temperature. Trit values “0”, “1” and “2” are coded with 0V, 0.5V and 1.0V respectively. Functionality of the design is validated through extensive T-Spice transient-simulations applying all possible dynamic test-patterns using PWL input-source of Tanner EDA V.16. Next, post-layout performance is analysed and compared. Process-Voltage-Temperature analysis is performed on: 1.1V supply-rail for fast-MOSFET, 1.0V supply-rail for typical-MOSFET and 0.9V supply-rail for slow-MOSFET in the temperature −40 ​°C–100 ​°C.