Efficient synthesis of distributed vector multipliers

Abstract

Direct hardware implementation of large inner product operations are always difficult because of the complexity of the multiplier modules. The paper suggests a new multiplier synthesis method for this type of arithmetic operation. The fully concurrent, bit serial vector multiplication architecture is intended for FPGA or ASIC implementation. The bit level optimization algorithm exploits the inherent bit pattern coincidences of the multiplier coefficients and using the deepest descent iteration steps, generates the minimal hardware implementation of the vector multiplications. The merged, distributed arithmetic module results in more than 30% resource savings. Higher bit clock rate can be achieved due to the smaller area and reduced average fanout. An example digital FIR filter architecture is synthesized using the algorithm and implemented on the Xilinx 4000 FPGA family.