Efficient state-dependent power model for multi-bit flip-flop banks

Abstract

Power consumption is one of the major issues in System-on-Chip (SoC) design with advanced semiconductor technologies for low power applications such as mobile phones. Recently, banking several 1-bit flip-flops has been proposed as a solution to reduce the power consumption in clock networks. For this purpose, to build an accurate power model for multi-bit flip-flop banks is required. However, it is an excessively time-consuming and sophisticated work due to a high number of pins. Therefore, we first propose a simplified power characterization method to reduce characterization time. Then an efficient power modeling is introduced to create an accurate state-dependent power model for multi-bit flip-flop banks. Experimental results show that the proposed characterization method allows to linearly increase CPU time with 1.3X per bit comparing with exponentially increasing CPU time by the traditional characterization method. In addition, the proposed power modeling provides an average error of 6% compared to SPICE simulation results.