Efficient Signal Selection Using Fine-grained Combination of Scan and Trace Buffers

Abstract

Post-silicon validation is a critical part of integrated circuit design methodology. The primary objective is to detect and eliminate the bugs that has escaped pre-silicon validation phase. One of the key challenges in post-silicon validation is the limited observability of internal signals in manufactured chips. Leveraging on-chip buffers addresses this issue by storing some of the internal signal states during runtime. A promising direction to improve observability is to combine trace and scan signals - a small set of trace signals are stored every cycle, whereas a large set of scan signals are dumped across multiple cycles. Existing techniques are not very effective since they explore a coarse-grained combination of trace and scan signals. In this paper, we propose a fine-grained architecture that addresses this issue by using various scan chains with different dumping periods. We also propose an efficient algorithm to select beneficial signals based on this architecture. Our experimental results demonstrate that our signal selection algorithm can improve restoration ratio up to 91% (32.3% on average) compared to existing trace only techniques. Our approach also shows up to 116% improvement (54.7% on average) compared to techniques that allows combination of trace and scan signals.