Efficient SBT Architecture for HEVC

Abstract

AbstractIn this paper report a different VLSI area efficient integer transform is designed for the High Efficiency video coding (HEVC) encoder. This integer transform built depends on Signed Biplane Transform (SBT) matrix. Which are extracted from the bit plane slicing of the integer transform grids in HEVC. This can be divided into different SBT matrices. Those SBT matrices consist of only zero, +1 and −1. Sum of all these SBT matrices is initial Integer Transform matrix. As SBT matrices contain only zero, +1 and −1 these matrices are simple and less bitwidth compare to the initial integer transform. In the structure SBT matrices most of elements are zero. This behavior of SBT is very advantages for preserving the arithmetic activities of SBT. In this paper converting large bitwidth of integer Transform can be converted into several low bit size of SBT matrices. Subsequently the area and delay of the circuit can be automatically decreased by using lower bit width of SBT matrices. SBT matrices contain only zero and +1 and −1 have adder reuse method is recommended for our Integer Transform. Because of this we can decrease the delay and area accurately. The design is usable for encoding HD video signals and finds application in mobiles and etc.KeywordsSBTHEVCVLSI systemBit plane methodInteger transform