Efficient reverse converter design for the new four-moduli set {22n, 2n + 1, 2n/2 + 1, 2n/2 – 1}

Abstract

This paper presents a new four-moduli set {22n, 2n + 1, 2n/2 + 1, 2n/2 – 1} (n even). According to new Chinese remainder theorem 1, an efficient algorithm is derived for converting four residue numbers to binary. Then, the converter architecture is designed using shorter bit-width carry propagate adders to improve the hardware performance considerably. Compared with existing converters for related four-moduli sets, the proposed converter shows higher speed and lower power consumption. The proposed converter design with 64-bit width has been implemented on the basis of the Taiwan Semiconductor Manufacturing Company 90-nm CMOS process. The chip area is 1622 × 1657 μm2, and the working frequency is 116 MHz. The experimental results show that the proposed design achieves more than 26.9 and 18.4% savings in delay and power consumption, respectively. The converter also saves at least 39% in AD2 (area × delay2).