Efficient Power Consumption using Hybrid Emerging Memory Technology for 3D CMPs

Abstract

The development of computing systems, data analytics, and storages for big data computing has resulted in an increasing need for low-power computational platforms and high-performance efficiency, capable of adjusting the processing capability and storage domains. In this context, high performance acts as a critical issue in future CMPs with restricted of battery lifetime and power consumption. For future CMPs architecting, 3D stacking of Last Level Cache (LLC) has been recently introduced as a new methodology to combat the performance challenges of 2D integration. We propose an uncore hybrid LLC which takes advantage of emerging memory technologies. In the former phase, a reconfiguration unit premised on a simple convex formulation is used to forecast the running application’s bandwidth and selects a high-performance configuration aimed at the LLC. The experimental results showed a reduction in (average memory access time) AMAT 12% as compared to SRAM- cache for PARSEC benchmarks which lead to 88% minimization in power consumption on average.