Efficient Performance Evaluation of Multi-Core SIMT Processors with Hot Redundancy

Abstract

Redundancy is a well-known technique for improving yield and consequently reducing cost. Prior work has shown that at the architectural level, hot spare components not only increase yield (and reduce costs) when components are defective, but also improve performance. Hot spares, however, complicate system evaluation: the presence of defects affects what resources are available. Accurate performance evaluation thus requires the simulation of the entire population of resulting dice in order to determine the expected performance $E[P]$ of the system. While simply expensive for single system evaluation, it is intractable for design space exploration. We therefore introduce two $E[P]$ estimation techniques, $\hat{E}_{m}[P]$ and $\hat{E}_{s}[P]$ . $\hat{E}_{m}[P]$ evaluates the $m$ most likely configurations, and assumes the performance of all others is zero, reducing simulation by 93 percent. This remains computationally expensive for design space exploration when individual, detailed, simulations require hours. $\hat{E}_{s}[P]$ evaluates only the most likely configuration, and assumes its performance for all other configurations, reducing simulation by 98 percent, with no more than 2.6 percent error in $E[P]$ , sufficient for differentiating designs along the Pareto-optimal front during design space exploration. Consequently, designers may add redundancy, and evaluate system performance and cost, with no greater design effort than performance evaluation alone.