Efficient parasitic-aware hybrid sizing methodology for analog and RF integrated circuits

Abstract

In this paper, a highly efficient parasitic-aware hybrid sizing methodology is proposed. It involves geometric programming (GP) as the first phase, both single-objective and many-objective evolutionary algorithms (EA) as the second sizing phase. The circuit performance constraints and layout-induced parasitics are considered simultaneously right from the GP sizing phase, while the optimization accuracy is significantly improved in the EA sizing phase. The proposed methodology features an effective integration of layout information into both sizing phases. It has been used to optimize several high-performance analog and RF circuits in different CMOS technologies. The experimental results demonstrate high efficacy of our proposed parasitic-aware hybrid sizing methodology.