Efficient parallel testing: A configurable and scalable broadcast network design using IJTAG

Abstract

To meet high performance requirements, System-on-Chips (SoCs) may include multiple replicated copies of functional embedded cores. To reduce the time required to apply identical test data to these replicated cores, we designed a novel broadcast network architecture that harnesses IEEE Std 1687 (IJTAG). Our architecture provides highly configurable broadcast/multicast and daisy modes, allowing one to selectively apply test data to any combination of embedded modules. The broadcast network is also scalable, supports hierarchical network architectures, and can be easily interfaced with other IJTAG-compliant test architectures. The new broadcast network provides a trade-off between network reconfigurability and the programming overhead of the network reconfiguration bits. It saves up to 70–80% of the test time in a sample test data broadcast scenario compared to serial and prior broadcast IJTAG networks. Compared to a serial network, our broadcast network requires only one extra reconfiguration bit.