Abstract
This paper presents efficient parallel hardware algorithms for string matching. Two subproblems known as the exact matching and the k-mismatches problems are covered. Systolic array architectures are developed using dataflow algorithms. Forwarding and broadcasting mechanisms provide high-performance parallel solutions to these problems. Time complexities of these parallel algorithms are O(( n/ d)+ α), 0≤ α≤ m, where n and m represent lengths of reference and pattern strings ( n⪢ m) and d represents the degree of parallelism. The degree of parallelism is controllable by using a variable number ( d) of input (and output) streams. Special purpose VLSI chip design schemes are presented with a hierarchical and linear systolic array of cells. With the linear systolic array architecture, m identical PEs are needed for a serial design and d∗ m identical PEs are needed for a parallel design.
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