Abstract
Instruction Set Simulator (ISS) is one of powerful debug tools for the DSPs. However, the efficiency of the instruction set simulation is very low. The paper describes the implementation and the optimization of the instruction set simulation for ZW100 which was developed by CETC. The optimizations include the use of instruction cache which has been used widely and pre-execute method also be presented. These optimizations all improve the performance of the instruction set simulator.
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