Efficient Optimization and Hardware Acceleration of CNNs towards the Design of a Scalable Neuro inspired Architecture in Hardware

Abstract

Convolution Neural Networks (CNNs) are responsible for the major discoveries in image classification and they are considered as the core of most current computer vision systems. In the implementation of deep CNN, Field-Programmable Gate Arrays (FPGAs) offer a promising paradigm towards major leaps in computational performance while achieving high-energy efficiency. Although current CNN accelerations on FPGA have demonstrated good performance, one major issue is that previously proposed implementation do not achieve a good balance between latency, precision, and hardware complexity. In order to overcome this problem, this paper proposes a highly optimized FPGA implementation of a CNN, named NASH-CNN (Neuro-inspired ArchitectureS in Hardware for CNN). An application for handwritten digit recognition, based on MNIST dataset, is evaluated. The experiment shows that our implementation achieves better performance/accuracy/complexity balance when compared to previously proposed schemes.