Efficient Network on Chip (NoC) using heterogeneous circuit switched routers

Abstract

Network-on-Chip (NoC) architecture in recent years has been considered as the overwhelming communication solution to provide scalability in multi core systems over traditional bus-based communication architecture. There is an increased use of multi-core with NoC in embedded systems solutions. Energy efficiency in the Network-on-Chip (NoC) is one of the key challenges as these embedded systems are typically battery-powered. Router architecture impacts the performance of NoC. With increased interest towards circuit-switched routers, in this paper, we have proposed an area and energy efficient 5-port, 4 Lane circuit switched router using a CLOS network which presents the advantages of area and energy efficiency. To further improve energy efficiency of NoC, we use a hybrid architecture by mixing buffered and bufferless routers. Our results shows that by using CLOS switch network, we can gain 32% reduction in area and 26% reduction in power compared to Crossbar switch of the same size. Our comparison of using an 8×8 mesh heterogeneous router topology shows a reduction of 3% to 18% in silicon area and 10% to 15% in total power using bufferless routers compared to a fully buffered configuration.